The present invention relates generally to low-dropout voltage regulators (LDO voltage regulators), and more particularly to improvements which provide low noise at medium and high frequencies, fast settling of the regulated output voltage, and low power consumption.
Current consumption (and hence power consumption) of various digital logic circuits and especially other integrated circuits such as analog front end circuits, that are manufactured using various modern integrated circuit manufacturing processes can instantly, i.e., within a few picoseconds to a few nanoseconds, vary between zero and a large maximum value, e.g. 5 to 150 milliamperes. At the same time, very precise regulation is required for the supply voltages provided by voltage regulators to such digital logic circuits and other integrated circuitry such as analog front end circuits. Very low levels of noise at the signal frequency are required in the regulated supply voltages for some applications (e.g. radios and capacitive sensors), because such noise may become mixed with the main signals. Unfortunately, the circuitry needed to reduce the high noise levels may also reduce the accuracy of the circuits or systems to which the regulated supply voltages are applied. Low noise at high frequencies may be achieved with filtering by means of a load capacitor. To achieve the advantage of such filtering, the voltage regulator which provides the supply voltage must be slow, with bandwidth significantly below the signal band, e.g. 10 to 100 times lower than the signal band. At the same time, the regulated supply voltages for the above mentioned applications should be able to settle very rapidly to the required supply voltage value during recovery from large, very rapid changes in the amount of load current demanded by such applications.
Fast settling of an LDO voltage regulator output signal requires use of a fast voltage feedback loop. Unfortunately, this is opposed to the above-mentioned noise filtering, and requires that the LDO voltage regulator have a large current-supplying capability e.g., roughly 10 to 100 times the nominal or quiescent current of the LDO voltage regulator, in order to quickly charge and/or discharge the capacitance of the user application or load to which the regulated voltage is applied.
Known fast LDO voltage regulators including 2 feedback loops can achieve load settling times which are limited mainly by the maximum output current capability of the LDO voltage regulators. Multiple current gain boost paths are provided in a single gain stage in such known fast LDO voltage regulators. Prior Art FIG. 1 shows such an LDO voltage regulator 10-1 which can provide very fast-response load voltage regulation, with fast reaction times in response to step changes in the amount of current demanded by a load (e.g., a load such as integrated digital logic circuitry or a capacitive touch sensor to which the regulated voltage is applied) without substantially increasing the power consumption of the LDO voltage regulator, and without the need to use a large external load bypass capacitor. The fast LDO voltage regulator of Prior Art FIG. 1 is similar to the fast LDO voltage regulator shown in FIG. 2 of commonly assigned U.S. Pat. No. 7,633,280 entitled “Low Drop Voltage Regulator with Instant Load Regulation and Method” issued to Ivanov et al. Dec. 15, 2009.
Prior Art FIG. 1 shows a high-speed, low-power LDO voltage regulator 10-1 including an input stage having differentially coupled N-channel input transistors M0 and M1, P-channel active load transistors M2 and M3, and tail current source 4. LDO voltage regulator 10-1 also includes an output stage including P-channel pass transistor M7, N-channel pull-down transistor M5, N-channel cascode transistor M6, and a voltage source 11 which produces a constant bias voltage V0 on the gate of cascode transistor M6. A gain stage is coupled between the differential input stage and the output stage, and includes P-channel source follower transistor M4 and resistor R5.
The sources of input transistors M0 and M1 are connected to tail current source 4. The gate of input transistor M0 is connected to reference voltage Vref, and the gate of input transistor M1 is connected by conductor 5 to the junction between resistors R1 and R2. The sources of load transistors M2 and M3 and source follower transistor M4 are connected to regulated output voltage conductor 6 on which the regulated output voltage Vout is produced. The drains of input transistors M0 and M1 are connected by conductors 2 and 3 to the drains of active load transistors M2 and M3, respectively. The gates of load transistors M2 and M3 are connected to conductor 2 and their sources are connected to output conductor 8. Resistor R1 is connected between output conductor 8 and conductor 5, which is connected to the gate of input transistor M1, and resistor R2 is connected between conductor 5 and VSS so that resistors R1 and R2 form a voltage divider. The gate of source follower transistor M4 is connected by conductor 3 to the drains of input transistor M1 and active load transistor M3, and also is connected to one terminal of compensation capacitor C0. The source of source follower transistor M4 is connected to Vout by output conductor 8.
Output conductor 8 also is connected to the drain of pass transistor M7, the source of which is connected to VDD. Output conductor 8 also is connected to the drain of pull-down transistor M5, the source of which is connected to VSS. A load circuit 16 modeled as a parallel connection of a load capacitor CL and a load current source IL are connected to output conductor 8. A load circuit 16 may demand a load current that undergoes very fast, large-magnitude transitions. The gate of pass transistor M7 is connected by conductor 9 to the drain of cascode transistor M6 and to one terminal of a pull-up resistor R7, the other terminal of which is connected to VDD. The source of cascode transistor M6 is connected by conductor 6 to the gate of pull-down transistor M5. The gate of cascode transistor M6 is connected by conductor 18 to receive a bias voltage V0 on the (+) terminal of voltage source 11, the (−) terminal of which is connected to VSS. The drain of source follower transistor M4 is connected by conductor 6 to one terminal of resistor R5, the other terminal of which is connected to VSS.
LDO voltage regulator 10-1 of Prior Art FIG. 1 includes three feedback loops. A first “accuracy” feedback loop includes input transistors M0 and M1 and source follower transistor M4. A second feedback loop includes common-gate source follower transistor M4, pull-down transistor M5, cascode transistor M6, and pass transistor M7. A third feedback loop includes source follower transistor M4, resistor R5, cascode transistor M6, and pass transistor M7. Internal capacitor C0 provides compensation for the first feedback loop. Capacitor C0 also decreases the bandwidth of the “accuracy” feedback loop including transistors M0 and M1 and source follower transistor M4, thereby decreasing the overall peak-to-peak noise at the output of voltage regulator 10-1.
The constant bias voltage V0 on conductor 18 causes the current in cascode transistor M6 to be substantially increased as the voltage on conductor 8 is decreased enough to turn pull-down transistor M5 off, so as to maintain a minimum current in pull-down transistor M5. In LDO voltage regulator 10-1, accuracy is determined by the “slow” loop including transistors M0, M1 and M4. The bandwidth gm0/C0 (where “gm0” is the transconductance of transistor M0) and high-frequency settling is determined by the two “fast” loops including transistors M4 and M5 and M4, M6, and M7, respectively.
During a large step increase of the current demanded by the load 16, a large amount of current must be supplied by pass transistor M7. That requires the gate voltage of pass transistor M7 to rapidly decrease. But pass transistor M7 is very large and has a large gate capacitance, so a large amount of current must be rapidly drawn out of the large gate capacitance of pass transistor M7 so it can supply the large step increase in current demanded by load 16.
The large step increase in demanded load current causes the regulated output voltage Vout to rapidly decrease, and that decreases the current through source follower transistor MP4 and resistor R5. The decreased current through resistor R5 lowers the source voltage of cascode transistor M6 and causes it to turn on harder, thereby increasing its drain current and rapidly discharging the large gate capacitance of pass transistor M7 so as to rapidly turn it on and supply the step increase in the demanded load current.
If the load current demanded by load 16 undergoes a large step decrease, this causes Vout to rapidly increase because load 16 suddenly is not sinking the large current being supplied by pass transistor M7. Consequently, the source voltage of source follower transistor M4 increases, causing it to turn on harder. That causes the gate voltage of pull-down transistor M5 to rapidly increase, so pull-down transistor M5 immediately sinks the available charge from capacitance associated with output conductor 8, thereby allowing sufficient time for pass transistor M7 to decrease its drain current. The rate at which the amplified drain current produced by pass transistor M7 decreases is determined by its gate capacitance and the resistance of pull-up resistor R7. This is how voltage regulator 10-1 of Prior Art FIG. 1 responds very rapidly to a step decrease in the demanded load current from a large value to a small value.
However, regulator 10-1 does not have adequate high-frequency noise filtering based on load capacitance CL, and therefore it requires high current (and hence high power) to adequately lower the noise. The high-frequency filtering using the load capacitor is not efficient because of the high speed of the fast loop including source follower transistor M4 and the gate capacitance of pull-down transistor M5. There are several reasons for that filtering inefficiency. In order to achieve the high-frequency noise filtering (without benefit of the present invention), one technique that can be used is to make the load capacitor CL very large, but this expedient makes it necessary that the size of pull-down transistor M5 also be very large. However, larger the size of pull-down transistor M5, the more high-frequency noise is likely to be injected into regulator 10-1 through its power supplies. This is likely to substantially increase the cost of the integrated circuit chip. The resistance of resistor R5 may be reduced in order increase the current through source follower transistor M4. It would be necessary to reduce the current through pull-up resistor R7 and make both pull-up transistor M7 and pull-down transistor M5 very large. (If the resistance of resistor R5 is reduced, then more current flows through source follower transistor M4 and cascode transistor M6. The current that flows through source follower transistor M4 comes from pull-up transistor M7. The current from pull-up transistor M7 is split between source follower transistor M4 and pull-down transistor M5 (apart from transistors M2 and M3, of course). Therefore, increasing current in source follower transistor M4 means less current flows through cascode transistor M5. This increases the “on” resistance of pull-down transistor M5, which is undesirable. Since the current in cascode transistor M6 increases when the resistance R5 increases, that means the gate voltage of pull-up transistor M7 increases. Since it is a P channel transistor, the VGS voltage (gate-to-source voltage) of pull-up transistor M7 decreases, which means less current flows through pull-up transistor M7. Therefore, a reduction in the resistance R5 must be accompanied by a reduction in the resistance R7 to allow for more current through pull-down transistor M5.)
Unfortunately, due to the high speed of the fast loop (with bandwidth gm4/Cg5, where gm4 is the transconductance of source follower transistor M4 and Cg5 is the gate capacitance of pull-down transistor M5), the high-frequency filtering involving the load capacitor CL is not efficient, and high quiescent current is required in transistor M4 in order to adequately decrease high-frequency noise.
Thus, there is an unmet need for a voltage regulator and method which provide the combination of low noise at medium and high frequencies, very fast settling of the regulated output voltage, and low power consumption.
There also is an unmet need for a low-cost voltage regulator and method which provide the combination of low noise at medium and high frequencies, very fast settling of the regulated output voltage, and low power consumption.
There also is an unmet need for a voltage regulator and method which provide the combination of low noise at medium and high frequencies, very fast settling of the regulated output voltage, and low power consumption without use of an external resistor to accomplish filtering of high frequency noise from the regulated output voltage.